The invention relates to a test methodology and application for measurements and enhancements to multi-chip and single chip modules that are attached to interface wiring boards by a compression scheme that blocks direct access to input/output (I/O) locations.
As higher density connectors are implemented on systems, there is a growing demand for connector schemes that permit significant I/O densities while at the same time provide for excellent signal integrity interconnection to the next level of packaging. With the advent of Land Grid Array (LGA) compression connectors as defined by Thomas and Batts, the density and signal integrity problems are addressed. A new problem for suitable test interface to the I/O connections of a chip carrier now becomes apparent. The LGA connector requires an electrically insulated backing structure to counter balance the forces used to compress the chip carrier to the system board. In the common application of this arrangement, an insulator sheet of FR4 and metal plate are used, which by nature of their design, covers entirely the access to the connector area on the board and hence the inputs and outputs of the chip carrier. In most applications this is permissible, but when access is needed, as in system bring-up, device monitoring, or circuit measurements, it is necessary to provide access to those pin locations while maintaining excellent electrical measurement characteristics.
This invention addresses the access of measurement locations of system boards interfaces with the use of Land Grid Array compression connection schemes, while at the same time maintaining excellent high frequency electrical characteristic capabilities. It is also possible to carry the counter balance technique further and permit the attachment of two MCMs back to back with different or similar functions to co-exist in the same location on a system board.